1. Field of the Invention
This invention relates to the priority encoder used in semiconductor integrated circuits.
2. Description of the Related Art
FIG. 1 shows a conventional dynamic type 16-bit priority encoder.
/D15 to /D0 are the input signals. The input signals /Dn (n=15, 14, . . . , 0) are inputted to the precharge and discharge sections 1-n (n=15, 14, . . . , 0), respectively.
The precharge and discharge sections 1-n comprise N channel type MOS transistor Nn (n=15, 14, . . . , 0) and P channel type MOS transistor Pn (n=15, 15, . . . , 0).
The source and drain of MOS transistor Nn are connected to the carry-line 2, and to the gate, the input signal /Dn is inputted. The input signal /Dn serves as a control signal for switching MOS transistor Nn. The source of MOS transistor Pn is connected to the power supply VCC, and to the gate, the precharge signal /PR is inputted.
The drain of MOS transistor Pn is connected to the node 3-n (n=15, 14, . . . , 0). The node 3-n is a connection point of source and drain of MOS transistor Nn of precharge and discharge sections 1-n and source and drain of M0S transistor N(n-1) of precharge and discharge sections 1-(n-1).
However, the node 3-0 (that is, n=0) is a connection point of source and drain of MOS transistor M of precharge and discharge sections 1-0 and source and drain of MOS transistor M1 for discharge. Now, let the connection point of source and drain of MOS transistor of precharge and discharge sections 1-15 and source and drain of MOS transistor M2 for discharge be the node 3-16.
On the high-order bit (/D15) side, the source of P channel type MOS transistor P' is connected to the power supply VCC, and to the gate, the precharge signal /PR is inputted. The drain of MOS transistor P' is connected to the node 3-16.
The source and drain of MOS transistor M1 for discharge is connected between one end on the low-order bit (/D0) side of the carry-line 2 and the grounding point GND. The source and drain of MOS transistor for discharge is connected between one end on the high-order bit (/D15) side of the carry-line 2 and the grounding point GND.
Each of nodes 3-n (n=16, . . . , 0) is precharged to the "1" level (power supply potential VCC) because MOS transistors Pn (n=15, . . . , 0) and P' are turned on when the precharge signal /PR becomes the "0" level.
When the low-order bit is in the priority mode, because control signal PRHL becomes the "1" level and the control signal PRLH the "0" level, MOS transistor M2 is turned on and MOS transistor M1 is turned off.
When the high-order bit is in the priority mode, because control signal PRHL is on the "1" level and control signal PRLH on the "0" level, MOS transistor M2 is turned on and MOS transistor M1 is turned off.
Each of nodes 3-n (n=16, . . . , 0) is discharged to the "0" level (grounding potential) in accord with the level of the input signal /Dn (n=15, . . . , 0).
To the bit select encoder circuit 4, input signal /Dn and potential of node 3-n of each of the precharge and discharge sections 1-n are inputted, respectively. The bit select encoder circuit 4 outputs 4-bit encoding output signals Q3 to Q0.
The priority encoder of the above configuration has the carry-line constructed by the pass transistor. Consequently, the ratio of the priority encoder are to the whole chip area can be designed to be comparatively small. However, it has a disadvantage in that it takes time to discharge all nodes of the carry-line as the number of bits of the input signal increases.
Next description will be made on the operation of the priority encoder.
This priority encoder is capable for judging which bit of the input signals /Dn is on the "0" level.
First of all, the low-order bit priority mode is considered.
The precharge signal /RP reaches the "0" level and each node 3-n (n=16, . . . , 0) is precharged to the "1" level (power supply potential VCC). Thereafter, the control signal PRLH reaches the "1" level and the control signal PRHL to the "0" level, and MOS transistor M1 enters the ON condition and MOS transistor M2 the OFF condition.
And each node 3-n is discharged in accordance with the level of the input signal /Dn. For example, if the high-order bit (/D15) only is on the "0" level and other bits (/D14-/D0) are on the "1" level, nodes 3-0 to 3-15 are discharged successively.
Next discussion will be made on the high-order bit priority mode.
The precharge signal /PR reaches the "0" level and all nodes 3-n (n=16, . . . , 0) are precharged to the "1" level (power supply potential VCC). Thereafter, the control signal PRHL reaches the "1" level and the control signal PRLH the "0" level, and MOS transistor M2 enters the ON condition and MOS transistor M1 the OFF condition.
And all nodes 3-n are discharged in accordance with the level of the input signal /Dn. For example, if the low-order bit (/D0) only is on the "0" level and other bits (/D15-/D1) are on the "1" level, nodes 3-15 to 3-0 are discharged successively.
In this way, the conventional priority encoder has a disadvantage in that it takes long time to discharge when the most significant bit or the bit near the most significant bit only is on the "0" level in the low-order bit priority mode, or when the least significant bit or the bit near the least significant bit only is on the "0" level in the high-order bit priority mode.
This disadvantage becomes more conspicuous as the number of bits of the input signal /Dn increases to 32 bits (n=31, . . . , 0), 64 bits (n=63, . . . , 0), etc., causing a bottleneck in high-speed processing.
In this way, in the conventional priority encoder, as the number of bits of input signal increases, the discharge time increases and this increase in the number of bits causes a bottleneck of high-speed processing, constituting a disadvantage.